The RapidIO to AXI Bridge is a highly flexible and configurable IP used along with the native RapidIO Controller (GRIO) to provide RapidIO interface on one side and AXI interface on the system side.

The Serial RapidIO core supports the physical layer specification as defined in the RapidIO Specification Rev 1.2. The Serial RapidIO Physical Layer defines a ...

RapidIO products use established scalable, packet-switched, high-performance fabric to assist equipment designers with wireless infrastructure, edge networking, storage, scientific, and military and ...

LONDON A Serial RapidIO 2.1 endpoint soft IP core for the Lattice ECP3 FPGA family has been developed by Praesum Communications (Petaluma, Calif.). Lattice Semiconductor Corp. has licensed this IP ...

Description: - SONET/SDH with FEC - 10G Base X, R and W - 100 BaseX, GE, Fibre channel - Clock Generation and Distribution for back plane Interface: - TDM, Telecom Bus, Utopia, SBI - Rapid-IO, ...